Conventionally, a timing generator having a timing vernier has been utilized for generating a pulse of a desired timing and suitably altering the timing as the occasion demands. In this type of timing generator, a period clock is ordinarily supplied to the generator, and a desired timing pulse is generated at the instant when a predetermined time has elapsed from an edge of the period clock.
FIG. 1 shows a conventional timing generator having such a timing vernier. The timing generator shown in FIG. 1 comprises a counter 1 which receives a period clock PC and a master clock MC, and a timing vernier 2, connected to the counter 1 in series, for delaying an output signal of the counter 1 for a suitable delay time and outputting the delayed signal therefrom. The counter 1 counts the master clock MC whose cycle (frequency) is an integer multiple of a cycle (frequency) of the period clock PC every period (i.e., the time interval between successive or neighboring period clocks). The timing vernier 2, on the other hand, is a timing-variable delay capable of delaying any pulse in a period for a desired time.
In the timing generator as shown in FIG. 1, a non-minute timing (rough timing) is determined by the counter 1 on the basis of the time interval of the master clock MC and a fine timing (a minute timing) is further determined on the basis of a delay time which is set by the timing vernier 2. Thus, a desired timing pulse is obtained on the basis of a combination of the rough timing and the minute timing.
The timing data which are set in the counter 1 and the timing vernier 2 are both rewritten every period clock PC by a timing data latch 3, and a desired timing pulse is generated while the timing is altered every period. That is, a train of period clocks PC and a train of master clocks MC whose cycle is an integer multiple of the cycle of the period clock PC are input to the counter 1. One or more of the input master clocks MC for actuating the timing vernier 2 is specified for every input of clocks PC and MC, and then the specified master clock MC (or the specified number of periods of master clock MC) is outputted to the timing vernier 2. In the timing vernier 2, delay-time data is loaded in accordance with the specified number of periods of the master clock MC needed to output a desired timing pulse with a predetermined time delay. In the conventional timing generator as described above, if the counter 1 and particularly the timing vernier 2 are ideally actuated, a pulse can be generated at a desired timing as described above so that "timing on the fly" can be attained.
However, it is practically impossible to set a delay time (a time elapsed between input and output operations of a pulse) of the timing vernier 2 to zero. In other words, the minimum delay time between the input and output operations of the timing vernier 2 has a positive finite value. Therefore, the conventional timing generator using the timing vernier has a disadvantage that the minimum delay time as described above degrades the performance of the timing generator as a dead time, and, as a result, a pulse is not necessarily generated at a desired timing.
An example of this dead time is illustrated in FIG. 2. As shown, a desired edge A is generated at a time point near to the end of a span (time interval of delay) TVS1 of the timing vernier which is set for a last master clock MC pulse in a period, and another desired edge B is generated within a next span (next time interval of delay) TVS2 of the timing vernier which is set for a first master clock MC in the next period. In addition, the edge A is generated after the first master clock MC in the next period for the edge B is formed. In this case, the timing vernier 2 is entirely devoted or exclusively used for the formation of the edge A until the edge A is formed and outputted. This devotion or exclusive use of the timing vernier 2 causes a dead time as represented by the minimum delay time TVmin in FIG. 2 during which the master clock MC for forming the edge B cannot be input to the timing vernier 2. For reference, TVmax and tA and tB represent the maximum delay time which can be set in the timing vernier 2 and delay times of the timing vernier 2, respectively.
The present invention has been proposed to overcome the above mentioned problems and has an object to provide a timing generator using a timing vernier in which substantially no dead time occurs and the timing can be altered at any time.